[Bug target/125611] [13/14/15 Regression] ICE: in extract_insn, at recog.cc:2894 (unrecognizable insn) with -O -mssse3 and __builtin_ia32_pmulhrsw128() since r6-6060

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125611

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-14 branch has been updated by Jakub Jelinek
<jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:2050bc6ba84815a8e6a9c6d9c6e04cd04c4ce66f

commit r14-12710-g2050bc6ba84815a8e6a9c6d9c6e04cd04c4ce66f
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Jun 6 09:50:35 2026 +0200

    i386: Fix up predicates on <ssse3_avx2>_pmulhrsw<mode>3, smulhrs<mode>3
expanders [PR125611]

    The following testcase ICEs since r6-6060-gacf93f1edc9 aka PR68991 fix.
    THe problem is that the commit has changed the predicates on
    *<ssse3_avx2>_pmulhrsw<mode>3<mask_name> pattern from nonimmediate_operand
    to vector_operand but kept the old predicates on the corresponding
    expanders.  With TARGET_AVX that makes no difference (so I've left
    the <ssse3_avx2>_pmulhrsw<mode>3_mask expander as is, that is only
    TARGET_AVX512BW && TARGET_AVX512VL), but without it if there is unaligned
    memory the expander can just expand it as memory without forcing into REG
    while the pattern will not match.

    2026-06-06  Jakub Jelinek  <jakub@redhat.com>

            PR target/125611
            * config/i386/sse.md (<ssse3_avx2>_pmulhrsw<mode>3,
smulhrs<mode>3):
            Use vector_operand instead of nonimmediate_operand.

            * gcc.target/i386/ssse3-pr125611.c: New test.

    Reviewed-by: Uros Bizjak <ubizjak@gmail.com>
    (cherry picked from commit 793da440da5c84090af9e864b824157db02cdc82)