[Bug rtl-optimization/125852] [16/17 Regression] Failure to late-combine address generation with load/store

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125852

--- Comment #2 from Drea Pinski <pinskia at gcc dot gnu.org> ---
The other thing I found with my changes to cfgcleanup(and other related
changes) was that it changes the EBB. So the it might the case the 2 basic
blocks are no longer part of the same EBB which is required for late combine
and cse and a few other rtl passes to work. 
I have not figured that part out yet either.