[Bug target/119760] GCC does not implement intrinsics for Vector Multiply-by-10 Unsigned Quadword and varients

[munroesj at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119760

--- Comment #6 from Steven Munroe <munroesj at gcc dot gnu.org> ---
(In reply to Kishan Parmar from comment #5)
> @Steven The Vector Multiply-by-10 Unsigned Quadword instruction appears to
> be separate from the other BCD operations. From the ISA description, it is
> just a
> operation (src<<3 + src<<1) on a 128-bit vector, which can be done using
> __int128.
> 
This can is used to convert BCD digits to binary. And is a vector __int128
operation. This is a single 3 cycle operation.

Could also use bcdctsq which is a 23 cycle operation that blocks the VSU for 12
cycles. It only converts 31-digits and requires valid sigh nibble. A full
32-digit (unsigned) convert requires at least one vmul10uq/vmul10euq.

The library implementation will choose based on the specifics (format of data
and number of digits required).

If the data is already in a Vector this is faster then transferring the data to
2x GPRs and the multiple step 64-bit add then add with carry.


> But other instructions you mentioned seem to be the decimal convert
> from/to National/Zoned formats. Are you suggesting that GCC should also
> provide builtins for these conversion instructions, in addition to the
> multiply-by-10 operation? And should it be adding bcd modes to gcc or
> similiar to how bcd add/sub were added using __int128?

I would expect build-ins for all operations defined in:
PowerISA 3.1C Section 6.15.2
Decimal Integer Format Conversion Instructions

I don't think we need to change the C language or add types. Just give library
developers access to these operation based on the vector __int128 type.