[Bug target/123584] [15/16 regression] armv8-a+sve2-sha3 ICE in extract_insn, at recog.cc:2888 (vxarq_u64) since r15-4270-g1dcc6a1a67165a

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123584

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kyrylo Tkachov <ktkachov@gcc.gnu.org>:

https://gcc.gnu.org/g:501baaf50c72a684000b077413e19635df598a86

commit r16-6922-g501baaf50c72a684000b077413e19635df598a86
Author: Kyrylo Tkachov <ktkachov@nvidia.com>
Date:   Thu Jan 15 05:22:46 2026 -0800

    aarch64: Adjust predicate used for SVE2 SHA3 XAR rotate amount

    While fixing the Advanced SIMD XAR patterns I looked at SVE2 and
    it looks okay there but the rotate amount should use the
    aarch64_simd_rshift_imm predicate rather than lshift_imm since the
    instruction (unlike the Advanced SIMD version) takes values from
    [1, bitwidth].

    Bootstrapped and tested on aarch64-none-linux-gnu.

    Signed-off-by: Kyrylo Tkachov <ktachov@nvidia.com>

    gcc/

            PR target/123584
            * config/aarch64/aarch64-sve2.md (@aarch64_sve2_xar<mode>): Use
            aarch64_simd_rshift_imm predicate for rotate amount.