[Bug target/123607] incorrect masked store vmovsh instruction emitted

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123607

--- Comment #5 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Looking at the Intel manuals, there are quite a few instruction forms which
only accept {k1} without {z},
VMOVSD m64 {k1}, xmm1
VMOVSS m32 {k1}, xmm1
VFPCLASSPD
VFPCLASSPS
VFPCLASSSD
VFPCLASSSS
VGATHERDPD
VGATHERDPS
VGATHERQPD
VGATHERQPS
VMOVSH m16{k1}, xmm1
VPCOMPRESSB m128{k1}, xmm1
VPCOMPRESSB m256{k1}, ymm1
VPCOMPRESSB m512{k1}, zmm1
VPCOMPRESSW m128{k1}, xmm1
VPCOMPRESSW m256{k1}, ymm1
VPCOMPRESSW m512{k1}, zmm1
VPGATHERDD
VPGATHERDQ
VPGATHERQD
VPGATHERQQ
VPSCATTERDD
VPSCATTERDQ
VPSCATTERQD
VPSCATTERQQ
VPTESTMB
VPTESTMW
VPTESTMD
VPTESTMQ
VPTESTNMB
VPTESTNMW
VPTESTNMD
VPTESTNMQ
VSCATTERDPD
VSCATTERDPS
VSCATTERQPD
VSCATTERQPS

Question is if those are all intentional case where they support masking but
not masking/zeroing.