[Bug target/123108] [16 Regression] RISC-V rv64gcvb: ICE at -O2/O3 during RTL pass: vsetvl

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123108

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|16.0                        |17.0

--- Comment #12 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Just an FYI, we had concluded to punt this to gcc-17 a couple weeks ago.  I
should have adjusted the milestone at that time.  It's not a complex change,
but it is extensive and the cost/benefit wasn't seen as good for gcc-16.