[Bug tree-optimization/124006] Improve another conditional sequence for RISC-V

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124006

--- Comment #4 from Drea Pinski <pinskia at gcc dot gnu.org> ---
So it turns out with my patch we get:

        lw      a4,0(a5)
        slliw   a3,a3,6 ;; 0 or 64
        andi    a4,a4,-897
        or      a3,a3,a4
        sw      a3,0(a5)

Which I think is reasonable here and maybe even better than what you were
describing. Jeff can confirm this is better than what you were thinking?

I think you were describing something like:
        lw      a4,0(a5)
        mov     a2, 64
        czero.eqz a3,a2,a3 ;; 0 or 64
        andi    a4,a4,-897
        or      a3,a3,a4
        sw      a3,0(a5)