[Bug target/119587] RISC-V: XTheadMemIdx: ICE on valid code with asm operands

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119587

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:c9586a3e9060cfcbda62604f515d9974c00adaea

commit r16-4380-gc9586a3e9060cfcbda62604f515d9974c00adaea
Author: Bohan Lei <garthlei@linux.alibaba.com>
Date:   Sat Oct 11 10:11:34 2025 -0600

    [PR target/119587] RISC-V: xtheadmemidx: Split slli.uw pattern

    The combine pass can generate an index like (and:DI (mult:DI (reg:DI)
    (const_int scale)) (const_int mask)) when XTheadMemIdx is available.
    LRA may pull it out, and thus a splitter is needed when Zba is not
    available.

    A similar splitter were introduced when XTheadMemIdx support was added,
    but removed in commit 31c3c5d.  The new splitter in this new patch is
    based on the removed one.

            PR target/119587
    gcc/ChangeLog:

            * config/riscv/thead.md (*th_memidx_operand): New splitter.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/xtheadmemidx-bug.c: New test.