[Bug target/121845] [Trunk] RISC-V rv64gcv: miscompile at -O0

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121845

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:62631c39a788161ff2f686adf355d10443e0d899

commit r16-4271-g62631c39a788161ff2f686adf355d10443e0d899
Author: Robin Dapp <rdapp.gcc@gmail.com>
Date:   Tue Oct 7 07:18:27 2025 -0600

    [PATCH] RISC-V: Detect wrap in shuffle_series_pattern [PR121845].

    Hi,

    In shuffle_series_pattern we use series_p to determine if the permute
    mask is a simple series.  This didn't take into account that series_p
    also returns true for e.g. {0, 3, 2, 1} where the step is 3 and the
    indices form a series modulo 4.

    We emit
     vid + vmul
    in order to synthesize a series.  In order to be always correct we would
    need a vrem afterwards still which does not seem worth it.

    This patch adds the modulo for VLA permutes and punts if we wrap around
    for VLS permutes.  I'm not really certain whether we'll really see a
wrapping
    VLA series (certainly we haven't so far in the test suite) but as we
observed
    a VLS one here now it appears conservatively correct to module the indices.

    Regtested on rv64gcv_zvl512b.

    Regards
     Robin

            PR target/121845

    gcc/ChangeLog:

            * config/riscv/riscv-v.cc (shuffle_series_patterns):
            Modulo indices for VLA and punt when wrapping for VLS.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr121845.c: New test.