[Bug target/122124] [16 Regression] RISC-V rv64gcv: miscompile at -O0

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122124

--- Comment #2 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:34ef2eec90baff5a7b84806fb0c7a5cef16b5350

commit r16-4270-g34ef2eec90baff5a7b84806fb0c7a5cef16b5350
Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
Date:   Tue Oct 7 07:14:01 2025 -0600

    [PATCH] RISC-V: Fix slide pattern recognition [PR122124]

    Ensure the second pivot is really a pivot and it's not in OP1.

            PR target/122124
    gcc/ChangeLog:
            * config/riscv/riscv-v.cc (shuffle_slide_patterns): Check if
            the second pivot is in OP1 and improve comments.

    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/rvv/autovec/pr122124.c: New test.