[Bug target/122486] RISC-V: The intrinsic for the vsetvli instruction generates assembly that does not match the intrinsic's documented semantics

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122486

Robin Dapp <rdapp at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |rdapp at gcc dot gnu.org

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
That's an optimization/canonicalization of SEW/LMUL, as 32/4 = 8/1.  The vsetvl
intrinsics docs say:

8.1. vsetvl
The vsetvl intrinsics return the number of elements processed in a stripmining
loop when provided with the element width and LMUL in the intrinsic suffix.
This pseudo intrinsic is typically mapped to vsetvli or vsetivli instructions.

The implementation must respect the ratio between SEW and LMUL given to the
intrinsic.  On the other hand, as mentioned in Section 5.2, the vsetvl
intrinsics do not necessarily map to the emission a vsetvli or vsetivli
instruction of that exact SEW and LMUL provided.  The actual value written to
the vl control register is an implementation defined behavior and typically not
known until runtime