[Bug target/119114] [14/15 regression] RISC-V: miscompile at -O3 since r14-4077-g86451305d8b

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119114

--- Comment #23 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Robin Dapp <rdapp@gcc.gnu.org>:

https://gcc.gnu.org/g:b58a0af4e2e28b395a3cb4b7283f16f05c0cf3c8

commit r15-8084-gb58a0af4e2e28b395a3cb4b7283f16f05c0cf3c8
Author: Robin Dapp <rdapp@ventanamicro.com>
Date:   Tue Mar 11 14:30:48 2025 +0100

    RISC-V: Mask values before initializing bitmask vector [PR119114].

    In the somewhat convoluted vector code of PR119114 we extract a
    <signed-boolean:1> mask value from a vector mask.  After some middle-end
    simplifications we end up with a value of -2.  Its lowest bit is
    correctly unset representing "false".  When initializing a bitmak vector
    from values we compare the full value/register against zero instead of
    just the last bit.  This causes erroneous mask values.

    This patch masks the values by & 0x1 before comparing against 0.

            PR target/119114

    gcc/ChangeLog:

            * config/riscv/autovec.md: Apply & 0x1 mask when initializing
            bitmask vector.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr119114.c: New test.