[Bug target/119224] RISC-V: sad 16x16 spilling since r15-6673-gb755c151fde4ad

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119224

--- Comment #1 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
b755c151fde4ad736405bb2e13a7de0420161179 is the first bad commit
commit b755c151fde4ad736405bb2e13a7de0420161179
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Tue Jan 7 14:28:25 2025 -0800

    RISC-V: vector absolute difference expander [PR117722]

    This improves codegen for x264 sum of absolute difference routines.
    The insn count is same, but we avoid double widening ops and ensuing
    whole register moves.

    Also for more general applicability, we chose to implement abs diff
    vs. the sum of abs diff variant.

    Suggested-by: Robin Dapp <rdapp@ventanamicro.com>
    Co-authored-by: Pan Li <pan2.li@intel.com>
    Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

            PR target/117722

    gcc/ChangeLog:
            * config/riscv/autovec.md: Add uabd expander.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr117722.c: New test.