[Bug target/120528] New: Optimize zero extend to TImode when value is in a VSX register on power10

[meissner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120528

            Bug ID: 120528
           Summary: Optimize zero extend to TImode when value is in a VSX
                    register on power10
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: meissner at gcc dot gnu.org
  Target Milestone: ---

Created attachment 61567
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=61567&action=edit
Test case for power10 to show the problem.

If you are compiling code for a power10, and you want to zero extend a DImode
value from memory to TImode and the target is in a vector register, the current
gcc compiler creates a TImode temporary in a GPR register pair and then uses
MTVSRDD to move both registers to the vector register.

I.e. if you compile the following code for -mcpu=power10:

void
mem_to_vsx_llong (unsigned long long *p, __uint128_t *q)
{
  __uint128_t x = *p;
  __asm__ (" # %x0" : "+wa" (x));
  *q = x;
}

It generates:

mem_to_vsx_llong:
        ld 2,0(3)
        li 3,0
        mtvsrdd 0,3,2
#APP
         # 0
#NO_APP
        stxv 0,0(4)
        blr

Instead it should generate:

mem_to_vsx_llong:
        lxvrdx 0,0,3
#APP
         # 0
#NO_APP
        stxv 0,0(4)
        blr

Similarly for SImode, it should generate lxvrwx, for HImode, it should generate
lxvrhx, and for QImode, it should generate lxvrbx.