[Bug target/123317] [16 Regression] RISC-V rv64gcv: miscompile at -Os

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123317

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Blocks|120763                      |
                 CC|                            |pan2.li at intel dot com

--- Comment #1 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Bisected to:

commit 6c8bcbc10d6cec60ed616cfffd08d2357baa4735
Author: Pan Li <pan2.li@intel.com>
Date:   Wed Oct 8 22:12:38 2025 +0800

    RISC-V: Combine vec_duplicate + vwsubu.wv to vwsubu.wx on GR2VR cost

    This patch would like to combine the vec_duplicate + vwsubu.wv to the
    vwsubu.wx.  From example as below code.  The related pattern will depend
    on the cost of vec_duplicate from GR2VR.  Then the late-combine will
    take action if the cost of GR2VR is zero, and reject the combination
    if the GR2VR cost is greater than zero.

[ ... ]

The only difference with that change in in func5().  I haven't debugged further
than that.


Referenced Bugs:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=120763
[Bug 120763] [meta-bug] Tracker for bugs to visit during weekly RISC-V meeting