[Bug target/121281] [15/16 Regression] RISC-V: Miscompile at -O3 since r15-7057-gd9d0eeea93d

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=121281

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #9 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Pan fixed this a few weeks ago:

commit 8615c855fa5647db11c84b882f0d88aadfc28863
Author: Pan Li <pan2.li@intel.com>
Date:   Thu Nov 20 08:16:10 2025 -0700

    [PATCH v1] RISC-V: Fix missed zero extend for unsigned scalar SAT_TRUNC
[PR122692]

    When the input of the scalar unsigned SAT_TRUNC is not Xmode,
    the rtx need to zero extend to Xmode before the underlying
    code gen.  Most of other SAT_* code gen has leveraged
    the API riscv_extend_to_xmode_reg but still have the ustrunc
    missed.  Then results in the failures mentioned in PR.

    The below test suites are passed for this patch series.
    * The rv64gcv fully regression test.

            PR target/122692