[Bug target/123108] [16 Regression] RISC-V rv64gcvb: ICE at -O2/O3 during RTL pass: vsetvl

[rdapp at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123108

Robin Dapp <rdapp at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |rdapp at gcc dot gnu.org

--- Comment #1 from Robin Dapp <rdapp at gcc dot gnu.org> ---
This is missing a "mode" attribute for a new vx variant.  However, after adding
it we're failing because we try to emit a vsetvl with the immediate VL "32",
instead of moving it to a register before.
My hunch is this happens because we decide for that vx variant very late, maybe
in post-reload late-combine and don't go the regular path.  Perhaps we need
more guardrails here.