[Bug target/123108] [16 Regression] RISC-V rv64gcvb: ICE at -O2/O3 during RTL pass: vsetvl

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123108

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |16.0
             Target|                            |riscv
           Keywords|                            |ice-on-valid-code