[Bug target/123010] RISC-V: 32-bit multiply by 2 generates slli+srai+slli and doesn't use slliw or addw

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=123010

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
addw has an implicit sign extend to 64bit mode.