[Bug tree-optimization/122635] RISC-V: -mrvv-vector-bits=zvl introducing unoptimal vsetivli zero,0 and insns depending on AVL nops

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122635

--- Comment #20 from Jeffrey A. Law <law at gcc dot gnu.org> ---
So Robin is currently testing a patch to address this problem.  It touches
gimple-folding, but it naturally is vector involved as well.  So the hope is
Richi can take a look before he goes on PTO for the rest of the year, but if
not, I can probably handle the review side.

We'll keep it on the tracker for a week or two so we can evaluate if a handoff
is needed.