[Bug target/122656] RISCV: ICE during RTL pass: expand

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122656

--- Comment #6 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:5fd09b47d9a75eb235ad46ebd206c4a870d64958

commit r16-5842-g5fd09b47d9a75eb235ad46ebd206c4a870d64958
Author: Robin Dapp <rdapp.gcc@gmail.com>
Date:   Tue Dec 2 13:00:51 2025 -0700

    [PATCH] RISC-V: Make vlsegff similar to vleff [PR122656].

    When we expand
      void d() { __riscv_vlseg2e32ff_v_i32mf2x2(&a, &c, b); }
    without a destination register we ICE because
    use_exact_insn wrongly adds arguments that we don't need and
      gcc_assert (opno == insn_data[icode].n_generator_args);
    triggers.

    Currently we expand a segmented fault-only-first load via use_exact_insn
    because its insn pattern wants a Pmode register as source.  We can't go
    the use_contiguous_load route because that one adds a vector-mode memory
    operand.

    It doesn't need to be like that, though, and this patch makes the
    segmented load similar to the regular FoF load in terms of source
    operand.  Also the patch only adds additional expansion arguments like
    the rounding mode only if the insn needs it and the number of operands is
    less than what we need, not unequal.

    Regtested on rv64gcv_zvl512b.

    Regards
     Robin

            PR target/122656

    gcc/ChangeLog:

            * config/riscv/riscv-vector-builtins-bases.cc: Use
            use_contiguous_load for vlsegff.
            * config/riscv/riscv-vector-builtins.cc
(function_expander::use_exact_insn):
            Only add rounding mode operand if insn requires it and number of
            arguments is < required.
            (function_expander::use_ternop_insn): Ditto.
            (function_expander::use_widen_ternop_insn): Ditto.
            * config/riscv/vector.md: Use vector-mode source operand.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr122656-1.c: New test.
            * gcc.target/riscv/rvv/base/pr122656-2.c: New test.`