[Bug target/122769] RISC-V: Short branch can be elided for alu op

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122769

--- Comment #13 from Jeffrey A. Law <law at gcc dot gnu.org> ---
The VRULL subreg bits are more for the outer expression code, not internal
expressions.  Your "a" and "b" look very much handleable -- and it's important
we do.

What we want to generate is something like

(set (reg:DI temp) (if_then_else (condition)
                          (reg:DI 138)
                          (const_int 0)))
(set (dest) (ashift:DI (reg:DI 137) (subreg:QI (reg:DI temp))

THe subreg doesn't really come into play.