[Bug target/122552] RISC-V: Cannot combine vector shift like vsll.vv to vsll.vx

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=122552

--- Comment #5 from Li Pan <pan2.li at intel dot com> ---
(In reply to Jeffrey A. Law from comment #4)
> Ah, that clarifies things.  Thanks Pan.
> 
> So ISTM that we want the initial pattern to match the .vv form, then an
> alternate pattern to match the vx form when combine decides the costs are
> such that the .vx form is cheaper?  Is that how the other cases are
> currently handled?

Yes, you are right.

> 
> The other approach one could try would be to define a predicate that accepts
> both forms, then use that in the named insn.  That would result in the
> initial code generation using whatever seemed the most appropriate from the
> vectorizer's viewpoint.  A predicate can actually match more than just a
> terminal node.  We use this a lot for matching variable shift counts for
> scalar ops.  Not sure if it'd help here, but I mention it just in case it
> might help.

I see, thanks Jeff, we may take care of this in the next stage 1 I think.