[Bug target/112817] RISC-V: RVV: provide attribute riscv_rvv_vector_bits for VLS codegen

[vineetg at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112817

Vineet Gupta <vineetg at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |ASSIGNED
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2024-03-06

--- Comment #14 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
To summarize this needs following 3 things

1. preprocessor macro __riscv_v_fixed_vlen if -march has explicit xxxvl
specified 
2. implement gcc toggle -mrvv-vector-bits=zvl which essentially copies the xxx
from -march string
3. Implement attribute riscv_rvv_vector_bits to specify vector length for user
types: cfr. https://godbolt.org/z/5Pc4PzPvs, https://godbolt.org/z/9hdMqh3jf,
https://godbolt.org/z/9WKM8s5rq