[Bug target/116125] New: RISC-V: Does not fully checking for overlapping memory regions

[sh.chiang04 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116125

            Bug ID: 116125
           Summary: RISC-V: Does not fully checking for overlapping memory
                    regions
           Product: gcc
           Version: 14.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: sh.chiang04 at gmail dot com
                CC: juzhe.zhong at rivai dot ai, kito at gcc dot gnu.org,
                    pan2.li at intel dot com, rdapp at gcc dot gnu.org,
                    rguenth at gcc dot gnu.org
  Target Milestone: ---

This test case is used to check whether the value stored in the memory is
correct when the memory overlaps.

compile option: -march=rv64gcv_zvl128b -mabi=lp64d -fno-inline -O3

testcase:

#include <stdlib.h>
#include <string.h>

struct st
{
  unsigned int num : 8;
};

void mem_overlap (struct st *a, struct st *b) {
  for (int i = 0; i < 9; i++) {
    a[i].num = b[i].num + 1;
  }
}

int main (void) {
  struct st * a;
  a = (struct st*) malloc (9 * sizeof(struct st));
  memset (a, 0, 9 * sizeof(struct st));

  // input a = 0, 0, 0, 0, 0, 0, 0, 0, 0
  mem_overlap(&a[1], a);

  // output a = 0, 1, 2, 3, 4, 5, 6, 7, 8
  if (a[2].num == 2)
    exit(0);
  else
    abort();
}

Following assembly shows, the first few instructions have checking for
overlapping memory regions. But some checks may be missing.

mem_overlap:
        csrr    a5,vlenb
        sub     a4,a0,a1
        slli    a5,a5,1
        addi    a4,a4,-7
        addi    a5,a5,-14
        bleu    a4,a5,.L2
        vsetivli        zero,8,e8,mf2,ta,ma
        vlseg4e8.v      v4,(a1)
        vid.v   v1
        vsll.vi v1,v1,2
        vadd.vi v4,v4,1
        vsuxei8.v       v4,(a0),v1
        lbu     a5,32(a1)
        addiw   a5,a5,1
        andi    a5,a5,0xff
        sb      a5,32(a0)
        ret
.L2:
        lbu     a5,0(a1)
        addiw   a5,a5,1
        sb      a5,0(a0)
        lbu     a5,4(a1)
        addiw   a5,a5,1
        sb      a5,4(a0)
        lbu     a5,8(a1)
        addiw   a5,a5,1
        sb      a5,8(a0)
        lbu     a5,12(a1)
        addiw   a5,a5,1
        sb      a5,12(a0)
        lbu     a5,16(a1)
        addiw   a5,a5,1
        ....

This error can also be reproduced in the master branch. Just revert following
patch.

commit e0b9c8ad7098fb08a25a61fe17d4274dd73e5145
Refs: basepoints/gcc-15-639-ge0b9c8ad709
Author:     Robin Dapp <rdapp@ventanamicro.com>
AuthorDate: Mon Feb 26 13:09:15 2024 +0100
Commit:     Robin Dapp <rdapp@ventanamicro.com>
CommitDate: Fri May 17 22:31:43 2024 +0200

    RISC-V: Add initial cost handling for segment loads/stores.

    This patch makes segment loads and stores more expensive.  It adds
    segment_permute_2 as well as 3 to 8 cost fields to the common vector
    costs and adds handling to adjust_stmt_cost.