[Bug rtl-optimization/86901] [AArch64] Suboptimal register allocation for int/float reinterpret

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86901

--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
But why not:

f2:
        fmov    w1, s0
        ubfx    w1, w1, 20, 11
        cmp     w1, 1015
        bhi     .L7
        fmul    s0, s0, s0
        str     s0, [x0]
        ret
.L7:
        b       g

?

There's no need to be using X regs here, W is just fine.