[Bug rtl-optimization/116009] [15 regression] ICE when building cython-3.0.10 on arm64 for Python 3.12 (insert_def_after, at rtl-ssa/accesses.cc:622)

[sjames at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116009

--- Comment #7 from Sam James <sjames at gcc dot gnu.org> ---
I have a sparc testcase too but I won't bother spending time on that unless you
want it.