[Bug target/115922] Missed optimization: MIPS: clear bit 15

[andrew at sifive dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115922

Andrew Waterman <andrew at sifive dot com> changed:

           What    |Removed                     |Added
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                 CC|                            |andrew at sifive dot com

--- Comment #1 from Andrew Waterman <andrew at sifive dot com> ---
Unlike MIPS, RISC-V's bitwise-logical instructions sign-extend their immediate
operands.  That's often beneficial, but in this case it renders the
optimization inapplicable.