[Bug target/115795] RISC-V: vsetvl step causes wrong codegen after fusing info

[jordi.sala at semidynamics dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115795

--- Comment #4 from Jordi Sala <jordi.sala at semidynamics dot com> ---
problem is this is not related to the vectorizer as far as I'm aware, so
setting -mrvv-max-lmul=m8 does not change the fact that vsetvl pass is going to
change the loads and stores from m8 to m2