[Bug target/115763] RISC-V: Use wrong SEW for vfmv.v.f when -march only has zvfhmin

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=115763

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:de9254e224eb3d89303cb9b3ba50b4c479c55f7c

commit r15-1822-gde9254e224eb3d89303cb9b3ba50b4c479c55f7c
Author: Pan Li <pan2.li@intel.com>
Date:   Wed Jul 3 22:06:48 2024 +0800

    RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]

    According to the ISA,  the zvfhmin sub extension should only contain
    convertion insn.  Thus,  the vfmv insn acts on FP16 should not be
    present when only the zvfhmin option is given.

    This patch would like to fix it by split the pred_broadcast define_insn
    into zvfhmin and zvfh part.  Given below example:

    void test (_Float16 *dest, _Float16 bias) {
      dest[0] = bias;
      dest[1] = bias;
    }

    when compile with -march=rv64gcv_zfh_zvfhmin

    Before this patch:
    test:
      vsetivli        zero,2,e16,mf4,ta,ma
      vfmv.v.f        v1,fa0 // should not leverage vfmv for zvfhmin
      vse16.v v1,0(a0)
      ret

    After this patch:
    test:
      addi     sp,sp,-16
      fsh      fa0,14(sp)
      addi     a5,sp,14
      vsetivli zero,2,e16,mf4,ta,ma
      vlse16.v v1,0(a5),zero
      vse16.v  v1,0(a0)
      addi     sp,sp,16
      jr       ra

            PR target/115763

    gcc/ChangeLog:

            * config/riscv/vector.md (*pred_broadcast<mode>): Split into
            zvfh and zvfhmin part.
            (*pred_broadcast<mode>_zvfh): New define_insn for zvfh part.
            (*pred_broadcast<mode>_zvfhmin): Ditto but for zvfhmin.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/scalar_move-5.c: Adjust asm check.
            * gcc.target/riscv/rvv/base/scalar_move-6.c: Ditto.
            * gcc.target/riscv/rvv/base/scalar_move-7.c: Ditto.
            * gcc.target/riscv/rvv/base/scalar_move-8.c: Ditto.
            * gcc.target/riscv/rvv/base/pr115763-1.c: New test.
            * gcc.target/riscv/rvv/base/pr115763-2.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>