[Bug target/113282] RISC-V non-atomic union store/load reordering

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113282

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
> On x86 this problem

Yes x86 does not enable the scheduler before ra and has less registers so the
scheduler is not as aggressive as on the other targets.

Note this is standard strict aliasing issue even. Which is definitely mentioned
as a non issue even.