[Bug target/114122] New: RISC-V: poor code generation in calling convention with vlen > 4096

[ewlu at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114122

            Bug ID: 114122
           Summary: RISC-V: poor code generation in calling convention
                    with vlen > 4096
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: ewlu at rivosinc dot com
  Target Milestone: ---

godbolt: https://godbolt.org/z/9bKPWYn65

For vector sizes with vlen > 4096, we generate more than 2x insns than
necessary for the function.

ex: (from godbolt link)
v256si_RET1_ARG3:
        li      a5,128
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v3,0(a2)
        vle32.v v1,0(a1)
        vle32.v v2,0(a3)
        addi    a1,a1,512 <-- all these addis are unnecessary
        addi    a2,a2,512
        addi    a3,a3,512
        addi    a4,a0,512
        vadd.vv v1,v1,v3
        vadd.vv v1,v1,v2
        vse32.v v1,0(a0) <-- Return value set here, can return now
        vle32.v v1,0(a1)
        vle32.v v3,0(a2)
        vle32.v v2,0(a3)
        vadd.vv v1,v1,v3
        vadd.vv v1,v1,v2
        vse32.v v1,0(a4)
        ret

Printing the gimple in the veclower2 (tree) pass, the optab_handler cannot find
an op which supports vlen 8192, which in turn generates vector constructors
that do not get completely optimized out.

 <constructor 0x7efc492554f8
      type <vector_type 0x7efc491b7a80 type <integer_type 0x7efc494435e8 int>
          sizes-gimplified asm_written BLK
          size <integer_cst 0x7efc4958bf60 constant 8192>
          unit-size <integer_cst 0x7efc4958bfc0 constant 1024>
          align:128 warn_if_not_align:0 symtab:1226528480 alias-set 1
canonical-type 0x7efc491b7a80 nunits:256
          pointer_to_this <pointer_type 0x7efc4921fa80>>
      length:2
      val <ssa_name 0x7efc492521f8 type <vector_type 0x7efc491b7690>

          def_stmt _10 = _8 + _9;
          version:10>
      val <ssa_name 0x7efc492522d0 type <vector_type 0x7efc491b7690>

          def_stmt _13 = _11 + _12;
          version:13>>