[Bug rtl-optimization/118067] [15 Regression] ICE: in lra_split_hard_reg_for, at lra-assigns.cc:1860 (unable to find a register to spill) {*lshrhi3_1} with -O -fno-split-wide-types -mavx512f

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=118067

--- Comment #3 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Uros Bizjak <uros@gcc.gnu.org>:

https://gcc.gnu.org/g:219ddae16f9d724baeff86934f8981aa5ef7b95f

commit r15-6394-g219ddae16f9d724baeff86934f8981aa5ef7b95f
Author: Uros Bizjak <ubizjak@gmail.com>
Date:   Fri Dec 20 16:16:15 2024 +0100

    i386: Disable SImode/DImode moves from/to mask regs without avx512bw
[PR118067]

    SImode and DImode moves from/to mask registers are valid only with
AVX512BW,
    so mark relevant alternatives in *movsi_internal and *movdi_internal as
such.

    Even with the patch, the testcase still fails, but now with:

    pr118067.c: In function âfooâ:
    pr118067.c:13:1: internal compiler error: maximum number of generated
reload insns per insn achieved (90)
       13 | }
          | ^
    0x2c3b581 internal_error(char const*, ...)
            ../../git/gcc/gcc/diagnostic-global-context.cc:517
    0xb68938 lra_constraints(bool)
            ../../git/gcc/gcc/lra-constraints.cc:5411
    0xb51a0d lra(_IO_FILE*, int)
            ../../git/gcc/gcc/lra.cc:2449
    0xaf9f4d do_reload
            ../../git/gcc/gcc/ira.cc:5977
    0xafa462 execute
            ../../git/gcc/gcc/ira.cc:6165

            PR target/118067

    gcc/ChangeLog:

            * config/i386/i386.md (*movdi_internal):
            Disable alternatives from/to mask registers without AVX512BW.
            (*movsi_internal): Ditto.