[Bug target/117990] [15 regression] RISC-V: Miscompile at -O3 zvl 256 since r15-4746-g30435cc2610

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117990

--- Comment #6 from Li Pan <pan2.li at intel dot com> ---
Add (mem:BLK (scratch)) to strided load define_insn can help to fix this issue,
as (mem:BLK (scratch)) is considered to alias all other memories.

In theory, we can do even more accurate alias analysis here, like verify each
location stride load touched.  Consider stage-3 and most RVV define insn
leverage the (mem:BLK (scratch)), it can add (mem:BLK (scratch)) to strided
load too here. I will test if there is any surprise.