[Bug target/96342] [SVE] Add support for "omp declare simd"

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=96342

--- Comment #15 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Tamar Christina <tnfchris@gcc.gnu.org>:

https://gcc.gnu.org/g:d069eb91d5696a8642bd5fc44a6d47fd7f74d18b

commit r15-6108-gd069eb91d5696a8642bd5fc44a6d47fd7f74d18b
Author: Victor Do Nascimento <victor.donascimento@arm.com>
Date:   Wed Dec 11 12:00:09 2024 +0000

    middle-end: add vec_init support for variable length subvector
concatenation. [PR96342]

    For architectures where the vector-length is a compile-time variable,
    rather representing a runtime constant, as is the case with SVE it is
    perfectly reasonable that such vector be made up of two (or more) subvector
    components of a compatible sub-length variable.

    One example of this would be the concatenation of two VNx4QI vectors
    into a single VNx8QI vector.

    This patch adds initial support for the enablement of this feature in
    the middle-end, removing the `.is_constant()' constraint on the vector's
    number of elements, instead making the constant no. of elements the
    multiple of the number of subvectors (which must then also be of
    variable length, such that their polynomial ratio then results in a
    compile-time constant) required to fill the vector.

    gcc/ChangeLog:

            PR target/96342
            * expr.cc (store_constructor): add support for variable-length
            vectors.

    Co-authored-by: Tamar Christina <tamar.christina@arm.com>