[Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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   Target Milestone|---                         |15.0
           Keywords|                            |wrong-code