[Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3

pinskia at gcc dot gnu.org gcc-bugzilla@gcc.gnu.org
Sun Dec 8 08:06:01 GMT 2024

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=117955

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
What version of qemu are you usirng?

Previous message (by thread): [Bug target/117955] New: [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3
Next message (by thread): [Bug target/117955] [15 Regression] GCC generate illegal riscv instruction `vsetvli zero,zero,e64,mf4,ta,ma` with -O2 and -O3
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