[Bug target/116278] [15] RISC-V: Miscompile at -O2 -fwrapv -fno-strict-aliasing

[pan2.li at intel dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=116278

--- Comment #7 from Li Pan <pan2.li at intel dot com> ---
The backend take 
rtx xmode_x = gen_lowpart (Xmode, x);

For the incoming op of .SAT_ADD, thus I think we should take lbu instead of lb
according to the ISA.