[Bug target/111461] [14.0 Regression] RISC-V rv32gc bootstrap ICEs with --enable-checking=rtl

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111461

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Patrick O'Neill <poneill@gcc.gnu.org>:

https://gcc.gnu.org/g:5b554c559d0103bfc1a68777907945ec3035a2bd

commit r14-4154-g5b554c559d0103bfc1a68777907945ec3035a2bd
Author: Patrick O'Neill <patrick@rivosinc.com>
Date:   Tue Sep 19 10:03:35 2023 -0700

    RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap

    Resolves PR 111461.

    during RTL pass: expand
    offtime.c: In function '__offtime':
    offtime.c:79:6: internal compiler error: RTL check: expected elt 0 type 'e'
or 'u', have 'w' (rtx const_int) in riscv_legitimize_const_move, at
config/riscv/riscv.cc:2176
       79 |   ip = __mon_yday[__isleap(y)];

    Tested on rv32gc glibc with --enable-checking=rtl.

    2023-09-19 Juzhe Zhong <juzhe.zhong@rivai.ai>

    gcc/ChangeLog:

            * config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate
            src_op_0 var to avoid rtl check error.

    Tested-by: Patrick O'Neill <patrick@rivosinc.com>