[Bug target/110751] RISC-V: Suport undefined value that allows VSETVL PASS use TA/MA

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110751

--- Comment #33 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Is it reasonable this way ?


ELSE VALUE = make_temp_ssa_name (vectype, NULL, "undefine_");

Then in the later "expand" stage:


defind_expand "cond_len_xxx"
...


if (REG_EXPR (operand) == "undefine") {
gen rvv insns with no else value
}

Is it reasonable?

Thanks.