[Bug target/112431] RISC-V GCC-15 feature: Support register overlap on widen RVV instructions

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112431

--- Comment #5 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:62685890d8861b72f812bfe171a20332df08bd49

commit r14-5982-g62685890d8861b72f812bfe171a20332df08bd49
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Wed Nov 29 18:53:06 2023 +0800

    RISC-V: Support highpart overlap for vext.vf

    PR target/112431

    gcc/ChangeLog:

            * config/riscv/vector.md: Support highpart overlap for vext.vf2

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Adapt test.
            * gcc.target/riscv/rvv/base/pr112431-4.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-5.c: New test.
            * gcc.target/riscv/rvv/base/pr112431-6.c: New test.