[Bug target/109977] [14 Regression] ICE: output_operand: incompatible floating point / vector register operand for '%d' at -Og since r14-215-g85279b0bddc1c5

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109977

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:a6a43a3b763816fec7c4eec6ae7be5b263dff340

commit r14-5840-ga6a43a3b763816fec7c4eec6ae7be5b263dff340
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Nov 25 10:30:39 2023 +0100

    aarch64: Fix up aarch64_simd_stp<mode> [PR109977]

    The aarch64_simd_stp<mode> pattern uses w constraint in one alternative and
    r in another, but for the latter incorrectly uses <vw> iterator in %<vw>1
which
    expands to %d1 for V2DF and %s1 for V2SF and V4SF (this one not relevant to
    the pattern) and %w1 for others, so it ICEs if the alternative is selected
    during final.  Compared to this, <vwcore> macro has the same values for all
    modes but uses w for V2DF and V2SF.

    2023-11-24  Andrew Pinski  <pinskia@gmail.com>
                Jakub Jelinek  <jakub@redhat.com>

            PR target/109977
            * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use
<vwcore>
            rather than %<vw> for alternative with r constraint on input
operand.

            * gcc.dg/pr109977.c: New test.