[Bug tree-optimization/112694] RISC-V: zve64d testing expose many ICE on C/C++ testing

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112694

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Andrew Pinski from comment #1)
> I am going to do a similar testing with -march=armv9-a+sve on aarch64 to see
> if there is similar ones for the vectorizer.

No, I think ARM SVE won't have those issues since their minimum VLEN of ARM SVE
is 128bit.

For RVV, when minimum VLEN is 128bit, all bugs (execution and ICE) are all
fixed.

This PR is bugs when minimum VLEN = 64bit which never happens on ARM SVE.