[Bug target/112599] RISC-V regression testsuite errors with rv64gcv_zvl1024b

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112599

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:d83013b88b74d1f1f774d94ca950d3b6dba26e5d

commit r14-5812-gd83013b88b74d1f1f774d94ca950d3b6dba26e5d
Author: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Date:   Fri Nov 24 07:18:00 2023 +0800

    RISC-V: Optimize a special case of VLA SLP

    When working on fixing bugs of zvl1024b. I notice a special VLA SLP case
    can be better optimized.

    v = vec_perm (op1, op2, { nunits - 1, nunits, nunits + 1, ... })

    Before this patch, we are using genriec approach (vrgather):

    vid
    vadd.vx
    vrgather
    vmsgeu
    vrgather

    With this patch, we use vec_extract + slide1up:

    scalar = vec_extract (last element of op1)
    v = slide1up (op2, scalar)

    Tested on zvl128b/zvl256b/zvl512b/zvl1024b of both RV32 and RV64 no
regression.

    Ok for trunk ?

            PR target/112599

    gcc/ChangeLog:

            * config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns):
New function.
            (expand_vec_perm_const_1): Add new optimization.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/autovec/pr112599-2.c: New test.