[Bug target/112478] riscv: asm clobbers not honored

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=112478

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:defa8681d951c6d6c43c71e3636ce4db9de04a28

commit r14-5526-gdefa8681d951c6d6c43c71e3636ce4db9de04a28
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Tue Nov 14 11:17:45 2023 +0800

    RISC-V: Save/restore ra register correctly [PR112478]

    We set ra to fixed register now, but we still need to save/restore that at
    prologue/epilogue if that has used.

    gcc/ChangeLog:

            PR target/112478
            * config/riscv/riscv.cc (riscv_save_return_addr_reg_p): Check ra
            is ever lived.

    gcc/testsuite/ChangeLog:

            PR target/112478
            * gcc.target/riscv/pr112478.c: New.

    Reviewed-by: Christoph Müllner <christoph.muellner@vrull.eu>
    Tested-by: Christoph Müllner <christoph.muellner@vrull.eu>