[Bug target/111720] RISC-V: Ugly codegen in RVV

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111720

--- Comment #28 from Richard Biener <rguenth at gcc dot gnu.org> ---
I tried to look up the requirements of __riscv_vle8_v_u8m2 in the vector
intrinsic specs but besides listing all those intrinsics the spec doesn't
contain _any_ documentation?  The 2nd arg is named 'vl' which I interpret
as vector length so that's so difficult for this intrinsic?  Why isn't it
just even a plain load?  I read the specified 'vl' isn't exact but the
intrinsics are still strongly typed, so a VLA typed gimple load should match
here?  And there should be a way to constrain the implementation somehow
since 'arr' has limited size.  Is the implementation constrained to use a
vector length <= the specified 'vl'?