[Bug rtl-optimization/91838] [8/9 Regression] incorrect use of shr and shrx to shift by 64, missed optimization of vector shift

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=91838

--- Comment #17 from Richard Biener <rguenth at gcc dot gnu.org> ---
Interestingly even with -mno-sse we somehow have a shift for V2QImode.  When
a scalar shift by precision is in the IL (for example via veclower) then
it's CCPs bit value tracking that makes it zero, if that's disabled then
VRP will compute it zero.  But we don't have any pattern that would
consistently do this.

I'm going to add one.