[Bug target/108840] Aarch64 doesn't optimize away shift counter masking

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108840

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2023-02-17
           See Also|https://gcc.gnu.org/bugzill |
                   |a/show_bug.cgi?id=91202     |
             Status|UNCONFIRMED                 |NEW
           Keywords|                            |missed-optimization

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed:

Trying 8 -> 10:
    8: r93:SI=r108:SI&0x1f
      REG_DEAD r108:SI
   10: r101:SI=r102:SI<<r93:SI#0
      REG_DEAD r102:SI
Failed to match this instruction:
(parallel [
        (set (reg:SI 101)
            (ashift:SI (reg:SI 102 [ *x_9(D) ])
                (subreg:QI (and:SI (reg:SI 108)
                        (const_int 31 [0x1f])) 0)))
        (set (reg:SI 93 [ _2 ])
            (and:SI (reg:SI 108)
                (const_int 31 [0x1f])))
    ])
Failed to match this instruction:
(parallel [
        (set (reg:SI 101)
            (ashift:SI (reg:SI 102 [ *x_9(D) ])
                (subreg:QI (and:SI (reg:SI 108)
                        (const_int 31 [0x1f])) 0)))
        (set (reg:SI 93 [ _2 ])
            (and:SI (reg:SI 108)
                (const_int 31 [0x1f])))
    ])
Successfully matched this instruction:
(set (reg:SI 93 [ _2 ])
    (and:SI (reg:SI 108)
        (const_int 31 [0x1f])))
Successfully matched this instruction:
(set (reg:SI 101)
    (ashift:SI (reg:SI 102 [ *x_9(D) ])
        (subreg:QI (and:SI (reg:SI 108)
                (const_int 31 [0x1f])) 0)))
rejecting combination of insns 8 and 10
original costs 4 + 4 = 8
replacement costs 4 + 8 = 12

The replacement cost should be still 8.