[Bug target/104688] gcc and libatomic can use SSE for 128-bit atomic loads on Intel and AMD CPUs with AVX

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688

--- Comment #21 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
What about loads?  That is even more important than the stores.  While atomic
store can be worst case done through cmpxchg16b, even when it is slower, we
can't use cmpxchg16b on atomic load because we don't know if the memory isn't
read-only.
As for the Write Back only vs. other types, doesn't that match the
" for cacheable" in the AMD statement?