[Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip

[vineetg at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106602

--- Comment #14 from Vineet Gupta <vineetg at rivosinc dot com> ---
(In reply to Jeffrey A. Law from comment #13)
> Trying 7, 8, 9 -> 10:
>     7: r140:DI=0x1
>     8: r141:DI=r140:DI<<0x26
>       REG_DEAD r140:DI
>       REG_EQUAL 0x4000000000
>     9: r139:DI=r141:DI-0x40
>       REG_DEAD r141:DI
>       REG_EQUAL 0x3fffffffc0
>    10: r137:DI=r138:DI&r139:DI
>       REG_DEAD r139:DI
>       REG_DEAD r138:DI
> Failed to match this instruction:
> (set (reg:DI 137)
>     (and:DI (reg:DI 138)
>         (const_int 274877906880 [0x3fffffffc0])))
> 
> 
> That's what we're looking for.  I think I had a wrong switch somewhere. 
> Match that with a define_split and you should be good to go.

I think you are missing the original left shift 6.
So insn 6 from my dumps is important if we are to match
zero_extendsidi2_shifted which matches and+shift (iff 3>>2==0xffffffff).

But it feels like you agree on using REG_EQUAL note (if avail) to created
merged pattern in try_combine() as opposed to my original thinking of only
doing it if regular pattern match failed.